A 28nm NavIC Chip Moves India Up the Semiconductor Value Chain

India built its own satellite-navigation constellation, NavIC, to avoid depending on foreign systems like GPS for positioning over the subcontinent. But a constellation is only half the battle; the other half is the chip inside the device that listens to it. On 19 January 2026, that side of the story took a notable step.

What happened

Hyderabad-based fabless design house MosChip Technologies announced it had completed an end-to-end, turnkey ASIC programme for ISRO's Space Applications Centre (SAC), delivering a custom system-on-chip in a 28nm process node and achieving successful silicon bring-up, the moment first chips come back from the foundry and are proven to work. The programme spanned design through a 10-layer FC-CBGA package and automated test-equipment (ATE) validation.

Why the node number matters

Much of India's deployed NavIC receiver silicon has historically sat on older, larger process nodes (think 110nm-180nm). Those work, but they are comparatively power-hungry and bulky. Moving a NavIC baseband to 28nm is the difference between a chip suited to industrial equipment and one that can disappear into a smartphone, a wearable, an IoT sensor or a car's telematics unit, drawing little power and costing little to integrate.

That is the unlock. For NavIC to graduate from a strategic asset into an everyday one, it needs receivers that mainstream consumer and automotive devices can adopt without penalty. A modern-node, low-power baseband is the enabler, and it dovetails with the government's push to have NavIC supported across handsets and with global chipmakers adding NavIC compatibility.

The capability behind the chip

The deeper significance is not one part; it is the demonstration of an indigenous design-to-validation capability. An "end-to-end turnkey ASIC" means the architecture, design, packaging and test were owned and executed domestically, with ISRO as the anchor customer. (The wafers themselves are still fabricated at an overseas 28nm foundry, the front-end fab India is building toward separately, but the high-value design, packaging and test work sits here.)

For investors, this points at two compounding trends: a maturing Indian fabless and ASIC-services sector that can win complex, strategic programmes, and the monetisation runway of the NavIC ecosystem as low-power silicon spreads into consumer and automotive markets. It also fits squarely within the India Semiconductor Mission and Design-Linked Incentive framework, which are explicitly trying to seed exactly this kind of high-end design muscle.