Mindgrove's RISC-V Secure SoC and the Pinetics Deal That Embeds It

Chennai-based Mindgrove Technologies has done something Indian fabless startups rarely manage: it has moved a domestically architected microcontroller off the datasheet and into a real commercial supply chain. On 14 May 2026 the company signed a two-year commercial partnership with Pune-based ODM Pinetics Technology Solutions, embedding its 28 nm Secure IoT System-on-Chip directly into Pinetics' system-on-module platforms. For a sector that has spent two decades doing design-services work for foreign principals, a homegrown SoC reaching a production design win is the more meaningful milestone — and the architectural choices underneath it are what make the deal worth dissecting.

The headline strategic decision is the instruction-set architecture. Mindgrove built the chip on the open-source RISC-V ISA rather than licensing an ARM Cortex core. That is not a cost-saving footnote; it is the load-bearing decision of the whole programme.

Why RISC-V is the load-bearing decision

An instruction-set architecture is the contract between software and silicon — the vocabulary of operations the processor understands. ARM's Cortex-M and Cortex-A families dominate the embedded world, but the cores are proprietary IP, licensed under per-design royalties and recurring per-unit fees. For a high-volume IoT or biometric device shipping in the tens of millions, those royalties compound into a structural cost on every unit. RISC-V, by contrast, is an open standard maintained by RISC-V International; the base ISA carries no licence fee, and a designer can implement the core, extend it, or buy a third-party implementation without paying a gatekeeper.

For an Indian company there is a second, sharper reason. ARM's IP — like most leading-edge processor IP — sits inside a Western export-control and licensing perimeter. Building national digital infrastructure on a foreign-licensed core means a foreign jurisdiction holds a veto over the substrate. RISC-V removes that exposure: the ISA is unencumbered, so the silicon under India's identity and telecom stack is not hostage to an export-control regime that can shift with geopolitics. That is the explicit logic Mindgrove has placed at the centre of its pitch, and it is why the choice matters more than the few dollars of royalty it saves.

The trade-off is honest and worth naming for any investor underwriting the thesis. ARM ships a mature, exhaustively validated toolchain, a vast library of pre-ported software, and a developer base measured in millions. RISC-V's ecosystem is younger; compiler support, debug tooling and silicon-proven peripheral IP are catching up but are not yet at parity. Mindgrove is betting that the ecosystem gap is closing faster than the cost-and-sovereignty advantage is eroding. The architecture targets the ~700 MHz class — comfortably above a simple controller, positioned for low-power edge-AI inference and on-device biometric processing rather than the kilohertz-to-low-megahertz duty of a basic embedded MCU.

Security and biometrics, fused into the die

The technically interesting part of the Secure IoT SoC is what Mindgrove has pulled onto the silicon itself. Hardware-level encryption modules and biometric recognition logic are integrated directly onto the die rather than implemented in software or bolted on as discrete companion chips.

The consequence is architectural, not cosmetic. Consider Aadhaar identity authentication, the workhorse transaction of India's digital public infrastructure. In a conventional edge device, a fingerprint or iris capture is digitised and shipped to a remote server for matching — a cloud round-trip that adds network latency, depends on connectivity, and widens the attack surface, because the biometric template traverses the network and lives, however briefly, outside the device. By performing recognition and encryption on-die, Mindgrove's SoC enables localised, low-latency authentication: the match happens in silicon, the sensitive template need not leave the chip boundary, and the round-trip and its exposure are eliminated. For a fingerprint terminal, a PoS device or a ration-distribution scanner deployed across a country with patchy connectivity, that is a materially better security and latency posture.

There is a parallel hardware-economics argument that engineers will recognise immediately. Consolidating discrete peripherals — crypto accelerators, the biometric front end, interface logic — onto a single die collapses what would otherwise be a multi-chip board. The benefits cascade: smaller PCB footprint, lower thermal output, and lower power draw, all of which matter disproportionately for battery-constrained or thermally constrained edge hardware. Fewer chips also means fewer inter-chip interfaces to secure, simplifying the trust boundary. Integration, here, is simultaneously a cost lever and a security lever.

The Pinetics deal and the 30% claim

This is where the 14 May 2026 Pinetics partnership becomes the proof point. Pinetics is an original design manufacturer (ODM) — it engineers the system-on-module (SoM) platforms that downstream OEMs drop into finished products. By embedding Mindgrove's RISC-V SoC into those SoM platforms, the partnership means a downstream OEM can adopt the Indian silicon without redesigning its own logic board: the integration work is absorbed once, at the module level, by Pinetics, rather than repeated by every device maker. That is exactly how silicon crosses the chasm from samples to volume — by living inside a reference module that removes the integration burden from the customer.

Mindgrove estimates the arrangement delivers roughly 30% lower device manufacturing cost versus imported silicon. The figure should be read as a vendor projection rather than an audited number, but the mechanism behind it is plausible: eliminated import duties and logistics, the BOM savings from on-die peripheral consolidation, and the avoided ARM royalty all push in the same direction. For an OEM weighing a switch, a credible double-digit cost delta plus a sovereign supply story is the combination that actually moves purchasing decisions.

The roadmap extends upward. Mindgrove has mapped a higher-tier Vision SoC aimed at computer vision, ADAS (advanced driver-assistance systems) and autonomous camera networks — a more demanding class of part that pushes the company from identity-and-IoT workloads toward real-time perception. The Design Linked Incentive (DLI) scheme has approved ₹15 crore for the Vision SoC, a signal that the government's chip-design subsidy is now backing specific Indian-designed parts rather than generic capacity.

Capital, foundry and the sovereignty thesis

Mindgrove has raised $10.3 million to date, including an $8 million commercial-launch round backed by Peak XV Partners, Rocketship.vc and Speciale Invest. The company is led by CEO Shashwath T R and CTO Sharan Srinivas J, and it operates fabless — it designs the silicon and outsources fabrication, today to TSMC. Critically, it is aligning future mass production to Tata's Dholera fab, the domestic foundry under construction in Gujarat. That sequencing is pragmatic: prove the design on a world-class foundry now, migrate to indigenous capacity as it matures, and avoid betting the product timeline on a fab that is not yet running.

The investor framing is the cleanest part of the story. The thesis is the indigenisation of silicon for India's digital public infrastructure and telecom — the identity, payments and connectivity rails that move a billion-plus people. Mindgrove is not trying to win the general-purpose MCU market on price against entrenched global incumbents; it is positioning a sovereign, RISC-V-based, security-integrated alternative for applications where provenance and on-device trust are the buying criteria, and where a domestic foundry path is a procurement advantage rather than a slogan.

The risks are real and should be underwritten honestly. The RISC-V software ecosystem still trails ARM; the 30% cost advantage is a company estimate; the Dholera migration depends on a fab that has yet to reach volume; and a two-year ODM partnership is a beachhead, not a market. But the shape of the bet is coherent — open ISA, on-die security, an ODM channel that removes integration friction, and a foundry roadmap that ends at home. For a country trying to own the silicon under its own identity infrastructure, that is a more durable position than another generation of design-services revenue.

Reporting per Biometric Update (12 and 14 May 2026), with additional detail from EdgeIR and StartupIntros.