India's Fabless Moment: 12nm Silicon, RISC-V Franchises and the DLI Scorecard

For years India's chip ambition was discussed in terms of fabs and packaging plants, the heavy industry of silicon. The quieter, capital-light story is fabless design, and in 2026 it is converting from policy promise to taped-out product. Two companies illustrate the shift, and a government scheme scorecard shows it is not isolated.

NETRA A2000 and the Mindgrove RISC-V franchise

Netrasemi, a Thiruvananthapuram firm backed by Zoho, has designed the NETRA A2000, described as India's first indigenous 12nm Edge-AI system-on-chip. Mass production at TSMC begins in 2026. The company has raised ₹125 crore, comprising a ₹107 crore Series A from Zoho and Unicorn India Ventures and ₹15 crore from the government's Design Linked Incentive (DLI) scheme. A 12nm Edge-AI SoC targets inference at the device edge, where power and latency budgets rule out sending data to the cloud, which is the fast-growing slice of AI silicon demand in cameras, industrial sensors and consumer devices.

Mindgrove Technologies, incubated at IIT Madras, is building a franchise on the open RISC-V instruction set, the royalty-free architecture that lets designers avoid Arm licensing fees and customise the core. Mindgrove shipped a Secure IoT 28nm microcontroller in 2024 and is following with the V2600, also called MG Vision, an edge-AI and hardware-security SoC aimed at CCTV and ADAS applications, with launch guided to late 2026. The company raised an $8 million Series A. Building on RISC-V is strategically deliberate: it lets an Indian startup own its core IP rather than rent it, and hardware-rooted security is a credible differentiator for surveillance and automotive customers.

The DLI scorecard

The reason these are not one-off stories is the policy machinery behind them. The DLI scheme's record to date shows 16 tape-outs, 6 ASICs, 10 patents and more than 1,000 engineers trained, supporting roughly 24 startups, of which 14 are VC-funded with about ₹430 crore raised. For FY26-27, the government is expanding the design-incentive envelope to ₹8,000 crore, which is expected to widen support to around 30 firms. Among the cohort, Morphing Machines, an IISc-linked team, has drawn ₹42 crore for its REDEFINE reconfigurable computing platform.

A tape-out, the point at which a finished design is committed to the foundry for fabrication, is the meaningful unit of progress here, because it marks the transition from simulation to silicon. Sixteen of them, with six reaching full ASIC status, is evidence that public design subsidies are producing real chips rather than slideware.

The fabless thesis

The investment logic is that fabless is where India's structural advantage, abundant design and verification engineering talent, meets a policy regime that de-risks the most expensive step. A tape-out and mask set at an advanced node can cost millions, a barrier that has historically killed Indian chip startups before first silicon. DLI grants and TSMC's merchant foundry access together remove that barrier, and private capital, Zoho, Unicorn India, and Series A venture money, is now following into the resulting companies.

The caveats are worth stating plainly. These are early-stage firms with products still ramping to volume, and "first indigenous" claims describe design origin, not domestic fabrication: NETRA's wafers are made at TSMC, not in India. Commercial success will be decided by design wins against entrenched global competitors, not by tape-out counts. But the pattern, policy de-risking converting into real silicon and drawing in private capital, is the clearest articulation yet of a credible Indian fabless thesis.